Deep Routing Congestion Estimator

In modern physical synthesis of VLSI circuits, routability has raised as a primary concern. So far, we have notice that the correlation between global routing (GR) estimation and detail routing (DR) is an essential issue when we want to make a design routable. In this project, We constructed a neural networks to apply supervised learning on congestion estimation. The model can predict the actual congestion and DRC in global routing stage or even embed into placement stage.